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Freescale Semiconductor Technical Data
Document Number: MC33390 Rev 7.0, 11/2006
Class B Serial Transceiver
The 33390 is a serial transceiver designed to provide bi-directional half-duplex communication meeting the automotive SAE Standard J1850 Class B Data Communication Network Interface specification. It is designed to interface directly to on-board vehicle microcontrollers and serves to transmit and receive data on a single-wire bus at data rates of 10.4 kbps using Variable Pulse Width Modulation (VPWM). The 33390 operates directly from a vehicle's 12 V battery system and functions in a logic fashion as an I/O interface between the microcontroller's 5.0 V CMOS logic level swings and the required 0 V to 7.0 V waveshaped signal swings of the bus. The bus output driver is short circuit current limited. Features * Designed for SAE J-1850 Class B Data Rates * Full Operational Bus Dynamics Over a Supply Voltage of 9.0 to 16 V * Ambient Operating Temperature of -40C to 125C * Interfaces Directly to Standard 5.0 V CMOS Microcontroller * BUS Pin Protected Against Shorts to Battery and Ground * Thermal Shutdown with Hysteresis * Voltage Waveshaping of Bus Output Driver * 40 V Max VBAT Capability * Pb-Free Packaging Designated by Suffix Code EF
33390
J-1850 SERIAL TRANSCEIVER
D SUFFIX EF SUFFIX (PB-FREE) 98ASB42564B 8-LEAD SOICN
ORDERING INFORMATION
Device MC33390D/DR2 -40C to 125C MCZ33390EF/R2 8 SOICN Temperature Range (TA) Package
VPWR
33390
+VBAT BUS LOAD
Primary Node
MCU
SLEEP TX RX 4X/Loop
GND
Secondary Nodes
Figure 1. 33390 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
33390 Bus Driver Voltage Regulator Thermal Shutdown
VBAT SLEEP
BUS
4.5 V Reference Waveshaping Filter Digital Output Driver 4X Enable Loopback
TX
RX
Loss of Ground Protection
LOAD
4X/LOOP
GND
Note This device contains approximately 400 active transistors and 250 gates. Figure 2. 33390 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
SLEEP GND LOAD BUS
1 1 2 2 3 3 4 4
88 77 66 55
RX TX 4X/LOOP VBAT
Figure 3. 33390 Pin Connections Table 1. 33390 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 9.
Pin Number 1 2 3 4 5 6 7 8 Pin Name SLEEP GND LOAD BUS VBAT 4X/ LOOP TX RX Definition Enables the transceiver when Logic 1 and disables the transceiver when Logic 0. Device ground pin. Accommodates an external pull-down resistor to ground to provide loss of ground protection. Waveshaped SAE Standard J-1850 Class B transmitter output and receiver input. Provides device operating input power. Tristate input mode control; Logic 0 = normal waveshaping, Logic 1 = waveshaping disabled for 4X transmitting, high impedance = loopback mode. Serial data input (DI) from the microcontroller to be transmitted onto Bus. Bus received serial data output (DO) sent to the microcontroller.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings VBAT DC Supply Voltage Input I/O Pins
(2) (1)
Symbol VBAT VI/O(CPU) VBUS VESD1 VESD2 TSTG TA TJ TPPRT RJ-A
Value -0.3 to 40 -0.3 to 7.0 -2.0 to 16
Unit V V V V
BUS and LOAD Outputs ESD Voltage
(3)
Human Body Model Machine Model Storage Temperature Operating Ambient Temperature Operating Junction Temperature Peak Package Reflow Temperature During Reflow (4), (5) Thermal Resistance (Junction-to-Ambient)
2000 200 -65 to 150 -40 to 125 -40 to 150 Note 5. 180 C C C C C / W
Notes 1. An external series diode must be used to provide reverse battery protection of the device. 2. SLEEP, TX, RX, and 4X / LOOP are normally connected to a microcontroller. 3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 4. 5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions of 7.0 V VBAT 16 V, -40C TA 125C, SLEEP = 5.0 V unless otherwise noted. Typical values reflect the parameter's approximate midpoint average value with VBAT = 13 V, TA = 25C. All positive currents are into the pin. All negative currents are out of the pin.
Characteristic POWER CONSUMPTION Operational Battery Current (RMS with Tx = 7.812 kHz Square Wave) BUS Load = 1380 to GND, 3.6 nF to GND BUS Load = 257 to GND, 20.2 nF to GND Battery Bus Low Input Current After SLEEP Toggle Low to High; Prior to Tx Toggling After Tx Toggle High to Low Sleep State Battery Current VSLEEP = 0 V BUS BUS Input Receiver Threshold (6) Threshold High (Bus Increasing until Rx 3.0 V) Threshold Low (Bus Decreasing until Rx 3.0 V) Threshold in Sleep State (SLEEP = 0 V) Hysteresis (VBUS(IH) - VBUS(IL), SLEEP = 0 V) BUS-Out Voltage (257 RBUS(L) to GND 1380 ) 8.2 V VBAT 16 V, Tx = 5.0 V 4.25 V VBAT 8.2 V, Tx = 5.0 V Tx = 0 V BUS Short Circuit Output Current Tx = 5.0 V, -2.0 V VBUS 4.8 V BUS Leakage Current -2.0 V VBUS 0 V 0 V VBUS VBAT BUS Thermal Shutdown
(7)
Symbol
Min
Typ
Max
Unit
mA IBAT (OP1) IBAT (OP2) - - 3.0 22.4 11.5 32 mA IBAT(BUS L1) IBAT(BUS L2) IBAT(SLEEP) - 38.2 65 - - 1.1 6.4 3.0 8.5 A
V VBUS(IH) VBUS(IL) BUSTH(SLEEP) VBUS(HYST) 4.25 - 2.4 0.1 3.9 3.7 3.0 0.2 - 3.5 3.4 0.6 V VBUS (OUT1) VBUS (OUT2) VBUS (OUT3) IBUS (SHORT) 60 129 170 A IBUS (LEAK1) IBUS (LEAK2) -500 - -55 189 - 500 C 150 TBUS (LI MHYS) 10 12 15 mA IBUS (LOSS) ILOAD (LOSS) - - 0.00 0.00 0.1 0.1 170 190 C 6.25 VBAT - 1.6 - 6.9 - 0.27 8.0 VBAT 0.7 mA
(Tx = 5.0 V, IBUS = -0.1 mA)
TBUS (LIM)
Increase Temperature until VBUS 2.5 V BUS Thermal Shutdown Hysteresis (8) TBUS (LIM) - TBUS (REEN) BUS and LOAD Current with Loss of VBAT or GND (IBAT = 0 A) (see Figure 4) -18 V VBUS 9.0 V -18 V VLOAD 9.0 V
Notes 6. Typical threshold value is the approximate actual occurring switch point value with VBAT = 13 V, TA = 25C. 7. 8. Device characterized but not production tested for thermal shutdown. Device characterized but not production tested for thermal shutdown hysteresis.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions of 7.0 V VBAT 16 V, -40C TA 125C, SLEEP = 5.0 V unless otherwise noted. Typical values reflect the parameter's approximate midpoint average value with VBAT = 13 V, TA = 25C. All positive currents are into the pin. All negative currents are out of the pin.
Characteristic BUS (CONTINUED) LOAD Output IL = 6.0 mA Unpowered LOAD Output VBAT = 0 V, IL = 6.0 mA TX Tx Input Voltage Tx Input Logic Low Level Tx Input Logic High Level Tx Input Current VTx = 5.0 V VTx = 0 V LOOP 4X / LOOP Input Current V4X / LOOP = 0 V (Normal Mode) V4X / LOOP = 5.0 V (4X Mode) 4X / LOOP Input Threshold (Tx = 4096 Hz Square Wave) Normal Mode to Loopback Mode Loopback Mode to 4X Mode RX Rx Output Voltage Low VBUS = 0 V, IRx = 1.6 mA Rx Output Voltage High VBUS = 7.0 V, IRx = -200 A Rx Output Current VRx = High; Short Circuit Protection Limits SLEEP
SLEEP Input Current
Symbol
Min
Typ
Max
Unit
LON - LDIO 0.3 0.56 0.9 0.07 0.2
V
V
V VTx(IL) VTx(IH) - 3.5 - - 0.8 - A ITx(IH) ITx(IL) 50 -2.0 106 0.23 200 2.0
A I4X / LOOP(IL) I4X / LOOP(IH) -200 -200 -60 110 200 200 V V4X / LOOP(IL) V4X / LOOP(IH) 1.1 3.2 1.31 3.43 1.5 3.6
VRx (LOW) 0.01 VRx(HIGH) 4.25 IRx 2.0 3.67 8.0 4.58 4.75 0.18 0.4
V
V
mA
A ISLEEP (IL) ISLEEP (IH) - 1.0 -0.23 6.21 -2.0 20
VSLEEP = 0 V VSLEEP = 5.0 V
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions of 7.0 V VBAT 16 V, -40C TA 125C, SLEEP = 5.0 V unless otherwise noted. Typical values reflect the parameter's approximate midpoint average value with VBAT = 13 V, TA = 25C. All positive currents are into the pin. All negative currents are out of the pin.
Characteristic BUS BUS Voltage Rise Time (9) (9.0 V VBAT 16 V, Tx = 7.812 kHz Square Wave) (see Figure 5) BUS Load = 3,300 pF and 1.38 k to GND BUS Load = 16,500 pF and 300 to GND BUS Voltage Fall Time (see Figure 5)
(9)
Symbol
Min
Typ
Max
Unit
tRISE (BUS) 9.0 9.0 tFALL (BUS) 9.0 9.0 tPWD (BUS) 35 tPD (BUS) - 17.7 25 62 93 10.50 11.17 15 15 11.15 11.86 15 15
s
(9.0 V VBAT 16 V, Tx = 7.812 kHz Square Wave)
s
BUS Load = 3,300 pF and 1.38 k to GND BUS Load = 16,500 pF and 300 to GND Pulse Width Distortion Time (9.0 V VBAT 16 V, Tx = 7.812 kHz Square Wave) (see Figure 6) BUS Load = 3,300 pF and 1.38 k to GND Propagation Delay Tx Threshold to Rx Threshold TX Tx to BUS Delay Time (Tx = 2.5 V to VBUS = 3.875 V) (see Figure 7) 4X Mode Normal Mode
SLEEP to Tx Setup Time (see Figure 7)
s
s
tTXDELAY - 13 tSLEEPTXSU 80 2.6 17.3 40 4.0 24 -
s
s
RX Rx Output Delay Time (Tx = 2.5 V to VBUS = 3.875 V) (see Figure 8) Low-to-Output High High-to-Output Low Rx Output Transition Time (CRx = 50 pF to GND, 10% and 90% Points) (see Figure 9) Low-to-Output High High-to-Output Low Rx Output Transition Time (10) (CRx = 50 pF to GND, SLEEP = 0 V, 10% and 90% Points) (see Figure 9) Low-to-Output High High-to-Output Low tRXTRANS / L-H tRXTRANS /H-L - - 0.32 0.08 5.0 5.0 tRXTRANS / L-H tRXTRANS /H-L - - 0.34 0.08 1.0 1.0 s TRXDELAY / L-H TRXDELAY / H-L - - 0.11 0.38 2.0 2.0 s s
Notes 9. Typical is the parameter's approximate average value with VBAT = 13 V, TA = 25C. 10. Rx Output Transition Time from a sleep state.
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ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES TEST FIGURES
33390 IBUS (LOSS) VBAT BUS -18 V to 9.0 V
SLEEP
2.5 V
Tx
tSLEEPTxSU
2.5 V
GND
LOAD
-18 V to 9.0 V ILOAD (LOSS) BUS
tTxDelay
3.875 V
Figure 4. Loss of Ground or VBAT Test Circuit
3.5 V Tx 0.8 V 64 s BUS
Figure 7. SLEEP to Tx Delay Times
122 s tRxDelay / lowto-output high
3.875 V
80% BUS 20% t RISE t FALL Rx
tRxDelay /high-tooutput low
2.5 V
Figure 5. BUS Rise and Fall Times
Figure 8. BUS-to-Rx Delay Time
5.0 V Tx 0V 90% tPWD(MIN) tPWD 1.5 V tPWD(MAX
)
64 s
tRXTRANS / L- tRXTRANS / H-L 90%
Rx 10%
10%
Figure 6. Pulse Width Distortion
Figure 9. Rx Rise and Fall Time
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33390 is a serial transceiver device designed to meet the SAE Standard J-1850 Class B performance for bidirectional half-duplex communication. The device is packaged in an economical surface-mount SOIC plastic package. An internal block diagram of the device is shown in Figure 2. The 33390 derives its robustness to temperature and voltage extremes from being built on a SMARTMOS process, incorporating CMOS logic, bipolar/MOS analog circuitry, and DMOS power FETs. Though the 33390 was principally designed for automotive applications requiring SAE J-1850 Class B standards, it is suited for other serial communication applications. It is parametrically specified over an ambient temperature range of -40C TA 125C and 7.0 V VBAT 16 V supply. The economical 8-pin SOICN surface mount plastic package makes the device a cost-effective solution.
FUNCTIONAL PIN DESCRIPTION Input Power (VBAT)
This is the only required input power source necessary to operate the 33390. The internal voltage reference of the 33390 will remain fully operational with a minimum of 9.0 V on this pin. Bus transmissions can continue with battery voltages down to 5.0 V. The bus output voltage will follow the battery voltage down and, in doing so, track approximately 1.6 V below the battery voltage. The device will continue to receive and transmit bus data to the microcontroller with battery voltages as low as 4.25 V. The pin can withstand voltages from -0.3 V to 40 V. If reverse battery protection is required, an appropriate diode must be placed in series with this pin to protect the IC. down resistor. No matter how many secondary nodes are on the Class B bus, the RC time constant of the Class B bus is maintained at approximately 5.0 s. The minimum and maximum capacitance and resistance on the Class B bus is given by the expressions shown in Table 5, page 10.
One Primary Node
10.6 k
470 pF
1.5 k
3300 pF
Sleep Input (SLEEP)
This input is used to enable and disable the Class B transmitter. The Class B receiver is always enabled so long as adequate VBAT pin voltage is applied. When the SLEEP pin voltage is 5.0 V, the Class B transmitter is enabled. If this input is 0 V, the Class B transmitter will be disabled and less than 65 A of current will be drawn by the VBAT pin. The pin also provides a 5.0 V reference, internal to the device, used to establish the Rx output level and slew rate times.
Figure 10. Minimum Bus Load
Primary Node
10.6 k
470 pF
1.5 k
3300 pF
24 Secondary Nodes
Class B Functional Description
The transmitter provides an analog waveshaped 0 V to 7.0 V waveform on the BUS output. It also receives waveforms and transmits a digital level signal back to a logic IC. The transmitter can drive up to 32 secondary Class B transceivers (see Figures 10 and 11). These secondary nodes may be at ground potentials that are 2.0 V relative to the control assembly. Waveshaping will only be maintained during 2 of the 4 corners when the 0 to 2.0 V ground potential difference condition exists. The 33390 is a secondary node on the Class B bus. Each secondary transceiver has a 470 10% pF capacitor on its output for EMI suppression purposes, as well as a 10.6 k 5% pulldown resistor to ground. The primary node has a 3300 10% pF capacitor on its output for EMI suppression, as well as a 1.5 k 5% pull-down resistor to ground. With more than 26 nodes, there is no primary node (see Figure 12). All nodes will have a 470 10% pF capacitor and a 10.6 k 5% pull442 11280 pF
Figure 11. Maximum Number of Nodes
31 Secondary Nodes
10.6 k
470 pF
342
14570 pF
Figure 12. Maximum Bus Load
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
Table 5. Class B Bus Capacitance and Resistance Expressions
Level Minimum Maximum Capacitance (3.3 x 0.9) + (0.47 x 0.9) = 3.39 nF (3.3 x 1.1) + 25 (0.47 x 1.1) = 16.55 nF Resistance to Ground (1.5 x 0.95) || (10.6 x 0.95) / 25 = 314 (1.5 x 1.05) || (10.6 x 1.05) = 1.38 k
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TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
Class B Module Inputs
Transmitter Data from the MCU (Tx) The Tx input is a push-pull (N-channel / P-channel FETs) buffer with hysteresis for noise immunity purposes. This pin is a 5.0 V CMOS logic level input from the MCU following a true logic protocol. A logic [0] input drives the BUS output to 0 V (via the external pull-down resistor to ground on each node), while a logic [1] input produces a high voltage at the BUS output. A logic [0] input level is guaranteed when the Tx input pin is open-circuited by virtue of an internal 40 k pulldown resistor. No external resistor is required for its operation. Waveshaping and 4X / Loop This input is a tristateable input: 0 V = normal waveshaping, 5.0 V = waveshaping is disabled for 4X transmitting, and high impedance = loopback mode of operation. This is a logic level input used to select whether waveshaping for the Class B output is enabled or disabled. A logic [0] enables waveshaping, while a logic [1] disables waveshaping. In the 4X mode, the BUS output rise time is less than 2.0 s and the fall time is less than 5.0 s (owing to the external RC pull-down to ground). In the loopback condition, the Tx signal is fed back to the Rx output after waveshaping without being transmitted onto the BUS. This mode of operation is useful for system diagnostic purposes.
Receiver Output to the Microcontroller (Rx) This is a 5.0 V CMOS compatible push-pull output used to send received data to the microcontroller. It does not require an external pull-up resistor to be used. The receiver is always enabled and draws less than 65 A of current from VBAT. The receive threshold is dependent on the state of the SLEEP pin. The receiver circuitry is able to operate with VBAT voltages as low as 4.25 V and still remains capable of "waking up" the 33390 when remote Class B activity is detected. When the SLEEP pin is 0 V and message activity occurs on the bus, the receiver passes the bus message through to the microcontroller. The 33390 does not automatically "wake up" from a sleep state when bus activity occurs: the microcontroller must tell it to do so. In the Static Electrical Characteristics table, the maximum voltage for Rx is specified as 4.75 V over an operating range of -40C to 125C temperature and 7.0 V to 16 V VBAT. This maximum Rx voltage is compatible with the minimum VDD voltage of microcontrollers to prevent the 33390 from sourcing current to the microcontroller's output. Switched Ground Output (LOAD) Normally this output is a saturated switch to ground, which pulls down the external resistor between the BUS and LOAD outputs. In the event ground is lost to the assembly, the LOAD output will bias itself "off" and will not leak more than 100 A of current out of this pin. Overtemperature Shutdown If the BUS output becomes shorted to ground for any duration, an overtemperature shutdown circuit "latches off" the output source transistor whenever the die temperature exceeds 150C to 190C. The output transistor remains latched off until the Tx input is toggled from a logic [0] to a logic [1]. The rising edge provides the clearing function, provided the locally sensed temperature is 10C to 15C below the latch-off temperature trip temperature. Waveshaping Waveshaping is incorporated into the 33390 to minimize radiated EMI emissions. Receiver Protocol The Class B communication scheme uses a variable pulse width (VPW) protocol. The microcontroller provides the VPW decoding function. Once the receiver detects a transition on Rx, it starts an internal counter. The initial "start of frame" bit is a logic [1] and lasts 200 s. For subsequent bits, if there is a bus transition before 96 s, one logic state is inferred. If there is a bus transition after 96 s, the other logic state is inferred. The "end of data" bit is a logic [0] and lasts 200 s. If there is no activity on the bus for 280 s to 320 s following a broadcast message, multiple unit nodes may arbitrate for control of the next message. During an arbitration, after the
33390
Class B Module Outputs
Transceiver Output (BUS) This is the output driver stage that sources current to the bus. Its output follows the waveshaped waveform input. Its output voltage is limited to 6.25 V to 8.0 V under normal battery level conditions. The limited level is controlled by an internal regulator/clamp circuit. Once the battery voltage drops below 9.0 V, the regulator / clamp circuit saturates, causing the bus voltage to track the battery voltage. A 1.5 k 5% external resistor (as well as any 10.6 k pull-down resistors of any secondary nodes) sinks the current to discharge the capacitors during high-to-low transitions. This sourcing output is short circuit-protected (60 mA to 170 mA) against a short to -2.0 V and sinks less than 1.0 mA when shorted to VBAT. If a short occurs, the overtemperature shutdown circuit protects the source driver of the device. In the event battery power is lost to the assembly, the bus transmitter's output stage will be disabled and the leakage current from the BUS output will not source or sink more than 100 A of current. The transceiver will operate with a remote ground offset of 2.0 V, but the lower corners of transmission will not be rounded during this condition.
Analog Integrated Circuit Device Data Freescale Semiconductor
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TYPICAL APPLICATIONS
"start of frame" bit has been transmitted, the secondary node transmitting the most consecutive logic [0] bits will be granted sole transmission access to the bus for that message. Loss of Assembly Ground Connection The definition of a loss of assembly ground condition at the device level is that all pins of the 33390, with the exception of BUS and LOAD, see a very low impedance to VBAT. The LOAD pin of the device has an internal transistor switch connected to it that is normally saturated to ground. This pulls the LOAD-side of the external resistor (tied from BUS to LOAD) to ground under normal conditions. The LOAD pin switch is essentially that of an "upside down" FET, which is normally biased "on" so long as module ground is present and biased "off" when loss-of-ground occurs. When a loss of assembly ground occurs, the load transistor switch is selfbiased "off", allowing no more than 100 A of leakage current
to flow in the LOAD pin. During such a loss of assembly ground condition, the BUS and LOAD pins exhibit a high impedance to VBAT; all other pins will exhibit a low impedance to VBAT. During this condition the BUS pin is prevented from sourcing any current or loading the bus, which would cause a corruption of any data being transmitted on the bus. While a particular assembly is experiencing a loss of ground, all other assembly nodes are permitted to function normally. It should be noted that with other nodes existing on the bus, the bus will always have some minimum / maximum impedance to ground as shown in Table 5, page 10. Loss of Assembly Battery Connection The definition of a loss of assembly battery condition at the device level is that the VBAT pin of the 33390 sees an infinite impedance to VBAT, but there is some undefined impedance between these pins and ground.
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TYPICAL APPLICATIONS PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98A listed below.
EF SUFFIX (PB-FREE) 8-LEAD SOIC NARROW BODY PLASTIC PACKAGE 98ASB42564B ISSUE U
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Analog Integrated Circuit Device Data Freescale Semiconductor
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REVISION HISTORY
REVISION HISTORY
REVISION 5.0
DATE 4/2006
DESCRIPTION OF CHANGES * * * * * * Converted to Freescale format Implemented revision history page. Added Part Numbers MC33390EF/EFR2 to Ordering Information on Page 1. Updates document form and style Removed MC33390EF and replaced with MCZ33390EF in the number Ordering Information Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 4. Added note with instructions to obtain this information from www.freescale.com.
6.0 7.0
10/2006 11/2006
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Analog Integrated Circuit Device Data Freescale Semiconductor
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MC33390 Rev 7.0 11/2006

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